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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The philosophy of open ISAs and the standardization efforts led by RISC-V International
- Understanding the RISC-V Mental Model: Load-Store Architecture, Register File, and Byte Ordering
- Evaluating trade-offs against ARM, x86, and POWER architectures for heterogeneous computing
- Assessing ecosystem maturity through key players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Mastering standardized interfaces: RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Navigating the Unprivileged Architecture specification, including CSR maps, exception handling, and memory hierarchies
- Utilizing RV32I / RV64I instruction sets to ensure cross-platform binary portability via ABI compliance
- Implementing memory ordering conventions and barrier instructions for multiprocessor environments
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Working with base integer (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Adapting programming strategies for 32-bit and 64-bit RISC-V targets
- Managing calling conventions and stack frames for embedded and real-time software systems
Compiler Toolchain Proficiency
- Leveraging the LLVM-based toolchain: Clang, LLVM, and Binutils for RISC-V cross-compilation
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
- Optimizing code using compiler intrinsics, adjustment levels, and profiling-driven tuning
- Navigating open-source toolchain workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Employing Rust for RISC-V systems programming: utilizing zero-cost abstractions, unsafe memory management, and bare-metal development
- Developing in No-Std environments with custom linkers, device drivers, and memory-mapped I/O
- Implementing Zephyr RTOS and Buildroot BSP for RISC-V targets
- Programming peripheral interfaces: GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Optimizing clock gating, power domain management, and low-power modes
- Analyzing cycle-accurate performance using simulation profilers and hardware counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Developing bootloader firmware using OpenSBI (based on the SBI specification)
- Implementing UEFI/EDK II on RISC-V for modern firmware boot stacks
- Porting Coreboot and U-Boot to RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: managing device tree overlays, CPU topology, and AIA interrupt controller drivers
- Developing vendor BSPs and configuring kernels for custom SoC platforms
- Enabling file system support, networking stacks, and containerization (Docker, Kubernetes) on RISC-V hosts
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Applying Network-on-Chip (NoC) design methodologies for multi-core RISC-V processors
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IP from OpenCores, the ChIPS Framework, and vendor RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores (e.g., BOOM, VexRiscv, PULP) on FPGA
- Conducting functional verification using SystemVerilog Assertions (SVA) and UVM methodologies
- Utilizing formal verification tools and property-based testing for core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Accelerating vector load/store, vector-fused multiply-add (VFMA), and matrix computations
- Optimizing workload-specific SIMD execution through variable-length vector operations (VL, VLEN)
- Leveraging vector mask operations, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing custom accelerators via custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends for custom instruction generation and code emission
- Strategizing hardware-software partitioning for accelerator integration in production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units using systolic arrays, tensor cores, and weight compression
- Applying model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
- Optimizing memory subsystems, including HBM/DDR bandwidth management for ML weights and activations
- Managing thermal and power budgets for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Architecting Secure Enclaves/TEEs for RISC-V: integrating OP-TEE and SEV-class trusted execution environments
- Securing the boot chain via root of trust, secure boot, and measured launch attestation
Cryptographic Acceleration
- Utilizing RISC-V cryptographic extensions (Zk, Zkr, K) for SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Integrating post-quantum cryptography (PQC) for next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastering ISA extension design: encoding, encoding tables, ABI impact analysis, and the RISC-V International submission process
- Designing custom register files with CBAR (Custom Base Address Registers) for operand dispatch
- Managing instruction pipelining, hazard detection, and pipeline modifications for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using directed versus constraint-random stimulus generation
- Implementing regression testing frameworks and coverage-driven verification for architectural changes
- Conducting interoperability testing to ensure custom instructions function within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for automotive processors
- Developing ASIL-Q classifications and safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and deterministic scheduling on multicore RISC-V platforms
- Developing Industrial IoT gateways with RISC-V: handling connectivity, edge analytics, and OTA firmware updates
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Defining architecture specifications: designing ISA extensions and core configurations for specific use cases
- Implementing RTL in SystemVerilog with UVM testbenches and formal verification coverage
- Performing FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Customizing Linux BSPs and toolchains for the custom RISC-V core
- Deploying AI workloads: integrating NPUs, applying model quantization, and benchmarking performance
- Validating security: enforcing PMP, secure boot, and benchmarking cryptographic acceleration
- Producing technical architecture documentation, analyzing IP strategy, and presenting to cross-functional teams
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
